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AXP223 datasheet pmic optimized for multi-core high-performance system r evision 1.1 2013.11.28
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 2 version history version date description 1.0 2013.08.30 first version 1.1 2013.11.28 modify some parameters supplemental register description
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 3 menu 0 summary ooooooooo oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo o oooooooooooo o d feature oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo o oooo w g typical application ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo / o frf diagram ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo & w pin description oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo p / functional block diagram ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo a n & absolute maximum ratings ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo a a p electrical characteristics ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo a d v control and operating ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo a & voao power on/off & reset oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo a & vodo power path management -gfr l oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo av vogo adaptive scia i m dum oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo d a vooo multi-power outputs oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo o oooooooooooooo d o vowo .hiedu ? fuel gauge system ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo ooo oooooooooooooooooooo o oooooooooooooooooo d / vo/o multi-function pin description oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo oo oooooooooooooooooo d / vo&o rmum oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo oo ooooooooooooooooooooo d / vopo gftummelt mucifram oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo o ooooo d & an registers oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo dp anoao registers list oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo dp anodo registers oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo g n package oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo w /
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 4 1 ldrrn3c ).9tte 54 g245072g a6 c2 n m50moc(57a203na2g b6/23 4c4a2r rn7n02r27a do _ amna 54 6ba5r52g t63 nbbo5vna5674 32d53570 4570o2( v2oo 5(cnaa23c n5(d6796ocr23p n7g rdoa5bo2 6dabda io(io v6723a234 _ da 54 6tt23570 n7 2n4c(a6(d42 n7g to25co2 v6rbo2a2 46oda567 /m5vm vn7 tdooc r22a am2 57v32n4570oc v6rbo25ac 6t nvvd3na2 b6/23 v67a36o 32d532g cc r6g237 nbbo5vna567 b36v24463 4c4a2r s ).9tte v6rb35424 n lesa(o6r b na5co2 yon4m omn 3 023 /m5vm 2tt5v527vc db a6 mw _ omn30570 vd3327a db a6 tsu) ldbb63a4 tu( /nc b6/23 6dabda o67an574 t52 m50m(vd3327a ioio _ m 50m 2tt5v527vc db a6 mh _ d7vodg24 6oan02 vd3327a a2rb23nad32 r675a63570 n7g 6am23 rdoa5(vmn772o ut(5a )io k6 0dn3n7a22 am2 4ntac n7g 4anc5o5ac 6t b6/23 4c4a2r _ ).9tte mn4 57a203na2g n356d4 b36a2va567 v53vd5a4 4dvm n4 23 6oan02 936a2va567n19p7g23 6oan02 936a2va567n19p 23 a 2rb23nad32 b36a2va567nk9p 23 vd3327a b36a2va567no9p 9n3a5vdon3 i(pnd02 u td2o pnd02 4c4a2r 45075t5vn7aoc 32gdv570 am2 cnaa23c bn3nr2a234 a24a570 b36v244 /m5o2 274d32 m50m(b32v54567 r2n4d32r27as ).9tte b 365g2 n tn4a 57a23tnv2 _ n oo6/4 am2 4c4a2r a6 ngd4a am2 6dabda 6oan02 gc7nr5vnooc _ n7g v663g57na2 nbbo5vna567 b36v24463 4c4a2r a6 nvm522 rdoa5bo2 r6g24 6t v672345672a27g cnaa23c d4570 a5r2 rn5rdrs ).9tte d7 a 2oo5027a 9 6 / 23 l2o2va d9l u v 53vd5a vn7 g54a35cd2 2o2va35v 27230c 42vd35ac a3n74bn327a 57 l n7g 2a237no )o ngnba23 5am5dr n7g nbbo5vna567 4c4a2r o6n g _ n7g 27nco24 nbbo5vna5674 4c4a2r /63570 /m27 67oc 2a237no b6/23 57bda cda /5am6da cnaa23cn63 cnaa23c g54vmn302 gnrn02ps ).9tte 54 nn5onco2 57 rrr rrr assh rr gr(b57 y bnvn02 ).9tte vn7 d42 67 waghcev 2 8ranv -hipe k 8ranv wm 2 l4vac garenau ncvna>iihce (b ni(b ] ni(b>c = e 2 ypvenvaprepv apt ytgavip iaghpe
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 5 2 y2nad32 96/23 hn7n02r27a nd9l u p 5g2 57bda 6oan02 tsm1gse1 n)he(ase1uu1p o67t50d3nco2 m50m 2tt5v527a d9l 4c4a2r )gnba52 l 63 )o(ngnba63 /5am 6oan02vd3327a(o5r5a nwsw1maar)haar)p ydooc d7a203na2g yon4m omn 3 023 d5oa(57 hlyik r n omn302 od3327a db a6 tsu) ldbb63a naa23c k2rb23nad32 h675a63570 ldbb63a l v6rbna5co2 vmn3023 8 50m b32v54567 o mn30570 _ 2 3363 54 o244 amn7 ash ash ldbb63a naa23c 6t 1n356d4 16oan02 4dvm n4 wsu1wst1wstt1wstw1 )da6rna5v omn302 936v2gd32 hn7n02r27a i532vaoc g352 ii a6 57g5vna2 vmn302 4anad4 )da6rna5vno 4vno570 6t vmn302 vd3327a nvv63g570 a6 am2 lc4a2r 6ng uw 6/(g36b6da 572n3 e20dona63 nip e k o 1 o o )o/nc4 67 ear) _ )iut 6/ 76542 i 6oan02 t36r ass1ese1 _ uaar14 a 2b g 352 vnbnc5o5ac eaar) )ie 6/ 76542 i 6oan02 t36r ass1ese1 _ uaar14 a 2b g 352 vnbnc5o5ac taar) i da i du 6/ 76542 i 6oan02 t36r ass1ese1 uaar14 a 2b g 352 vnbnc5o5ac ua ar) iiuiiu 6oan02 t36r ass1ese1 _ uaar14 a 2b g352 vnbnc5o5ac waar) iitiieiitiie 6oan02 t36r ass1ese1 _ uaar14 a 2b _ g 352 vnbnc5o5ac taar) iiw 6oan02 t36r ass1ese1 _ uaar14 a 2b _ g 352 vnbnc5o5ac uaar) iohi 6oan02 t36r ass1usw1 _ uaar14 a 2b g 352 vnbnc5o5ac taar) t l /5 a vm ioul e2454an7v2 ugar _ b6/23 t36r ioiou o8pii d7a237no 57a203na567 hl /5am uaar) g352 vnbnc5o5ac _ v n7 c2 d42g a6 g352 5c3na567 r6a63 n7g vmn302 ii h lc7vm3676d4 idv nio ( iop ioiou /5am 16oan02 t36r usg1esw1 uaar14 a 2b g 352 vnbnc5o5ac usw) ioiot /5am 16oan02 t36r asg1ushw1 tar14 a 2b g 352 vnbnc5o5ac t ) 4dbb63a570 16oan02 enrb o67a36on1eop ioioe /5am 16oan02 t36r asg1usrg1 tar14 a 2b g 352 vnbnc5o5ac t) ioiow /5am 16oan02 t36r asg1ushw1 tar14 a 2b g 352 vnbnc5o5ac asg) ioioh /5am 16oan02 t36r usa1tshh1 har14 a 2b g 352 vnbnc5o5ac t) i(pnd02 u yd2o pnd02 4c4a2r d5oa(57 m50m(b32v54567 gdno(r6g2 nda6rna5v r2a23570 4c4a2r 9365g24 m50m ngnbanc5o5ac t63 g5tt2327a cnaa23c d7g23 2 n4c r6g2 9365g2 m50m(b32v54567 r2n4d32r27a 6t 4b2v5t5v v2oo4 ntp d7g23 m50m(b32v54567 r6g2 9365g2 1n356d4 96/23 hn7n02r27a gnan 4dvm n4 k3n74527a 96/23 o674drba567nr) 63 rp _ e2rn57570 naa23c 5t2n 63 r)mp _ omn302 lana2np n7g omn302 k5r2 k/6(o22o 6/(96/23 n37570 936a2va567 9365g2 ).9t te i52 k2rb23nad32 864a d7a23tnv2 864a vn7 2vmn702 gnan /5am 9tdeln9d4m(9doo k /6 5 3 2 d7 a 2 3 tnv2 e 2gdv2g l235no d4p yo25co2 d7a233dba4 hn7n02r27a yo25co2 957 yd7va567 o67t50d3na567s t p9d vn7 c2 42a n4 d )io n7g 46 67 7(vm5b o67t50d3nco2 k5r23 ut e2054a234 t63 inan 4a63n02 gd3570 lc4a2r 96/23(6tt lc4a2r hn7n02r27a ldbb63a l6ta e242a n7g 8n3g e242a ldbb63a l6ta 96/23(6tt n7g 8n3g 96/23(6tt _ ldbb63a 2 a23 7 no n2db k3500234 9 e 57g5vna570 lc4a2r e242a 63 96/23(6tt ia237no 96/23 i2a2va567n9od057e2r6nod7dno5t52g i352 onbnc5o5ac p ldbb63a l6ta 96/23(67 t63 d7bda dabda 236oan027g236oan02 936a2va567 n1919p 23vd3327a 936a2va567 no9p 23 a2rb23nad32 936a2va567 n k9p 850moc d7a203na567 d7a237no e2t2327v2 16oan02 /5am 850m )vvd3nvc ash 7(vm5b hlyik
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 6 3 kcb5vno )bbo5vna567
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 7 4 957 i5n03nr
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 8 5 957 i24v35ba567 dr nr2 kcb2 o67g5a567 yd7va567 i24v35ba567
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 9 num name type condition function description
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 10 6 yd7va567no o6v i5n03nr
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 11 7 )c46oda2 hn5rdr ena5704 lcrc6o i24v35ba567 1nod2 75a4 ) od input voltage -0.3 ~ 11 v mln8 input voltage -0.3 ~ 11 v w a operating temperature range -20 ~ 80 c w b pgvip w er-enav n e sap4e -20~130 c wu storage temperature range -40 ~150 c w [y7l maximum soldering temperature (at leads 2 10sec) 300 c m y8l maximum esd stress voltage 2 human body model >4000 v ( l internal power dissipation 2700 mw
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 12 8 io2va35vno omn3nva2354a5v4 lcrc6o i24v35ba567 o67g5a567 hd k9 h). 75a4 a cin 1 d ) od d7bda 1 6oan02 esr gse 1 d k 1 k od3 3 27a ) n5onco2 2t6 3 2 6 ng570 ) k waar1 1 6oan02 i 3 6b eaaa r) 1 1 ) od 7g23 1 6oan02 6v 6da esr 1 1 k d9l u dabda 1 6oan02 tsm hsa 1 e ) od d7 a 237no dg2no e 2454an7v2 9d a 6 9d ) od a 6 d9lk uta rmr vbus 1 d 1l d7bda 1 6oan02 esr gse 1 d k 1 k od3 3 27a ) n5onco2 2t6 3 2 6 ng570 ) k waar1 1 6oan02 i 3 6b haa maa r) 1 1 1l 7g23 1 6oan02 6v 6da esr 1 1 k d9l u dabda 1 6oan02 tsm hsa 1 e 1l d7 a 237no dg2no e 2454an7v2 9d a 6 9d 1l a 6 d9lk usa rmr bat t e r y cha r ger 1 k e pk ) k omn 3 02 k n 3 02a 1 6oan02 (ash wst ash 1 d o8 e p omn 3 02 od3 3 27a utaa tuaa r) d ke k 35vo2 omn 3 02 od3 3 27a ua d o 8ep r) 1 ke k 35vo2 omn 3 02 km 3 24m6og 1 6oan02 esa 1 1 eio8p e 2vmn 3 02 na a 2 3 c km 3 24m6og 1 6oan02 km 3 24m6og 1 6oan02 e 2ona5 2 a 6 1 k ) e pik (uaa r1 k kdhieu omn 3 023 lnt2ac k5r23 k 23r57na567 k5r2 k 35vo2 h6g2 ha h57 k kdhiet omn 3 023 lnt2ac k5r23 k 23r57na567 k5r2 o o h6g2 wra h57 d ii i7g 6 t omn 3 02 d7g5vna567 od3 3 27a ena56 o1 h6g2 ua uh d o8 e p r) n tc o6og k 2rb23nad 3 2 y ndoa km 3 24m6og omn 3 02 tsuut 1 k a estgw 1 1 6oan02 i54vmn 3 02 esttg 86a k 2rb23nad 3 2 y ndoa km 3 24m6og omn 3 02 asems 1 k8 a estgw 1 1 6oan02 i54vmn 3 02 ash y noo570 1 ki k o i54nco2 km 3 24m6og 1 6oan02 km 3 24m6og ast 1 8c4 a 2 3 2454
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 13 symbol description condition min typ max units
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 14 symbol description conditions min typ max units m f y c y y v r t c_ v c c output v oltage i r t c_ v c c =1ma -1% 3.0 1% v i r t c_ v c c output cur r ent 30 ma tsulv v aldo1 output v oltage i aldo1 =1ma -1% 3.0 1% v i aldo1 output cur r ent 300 ma i q quiescent cur r ent 60 a psrr p o w er supply r ejection ratio i aldo1 =60m a ,1khz tbd db e n output noise,20- 80khz v o=3.3v , io=20ma 31 v rms tsule v aldo2 output v oltage i aldo2 =1ma -1% 2.5 1% v i aldo2 output cur r ent 300 ma i q quiescent cur r ent 62 a psrr p o w er supply r ejection ratio i aldo2 =10m a ,1khz tbd db e n output noise,20- 80khz v o=3.3v , io=20ma 31 v rms tsulr v aldo3 output v oltage i aldo3 =1ma -1% 3.0 1% v i aldo3 output cur r ent 200 ma i q quiescent cur r ent 60 a psrr p o w er supply r ejection ratio i aldo3 =10m a ,1khz tbd db e n output noise,20- 80khz v o=3.3 v , io=20ma 43 v rms usulv v dldo1 output v oltage i dldo1 =1ma -1% off 1% v i dldo1 output cur r ent 400 ma i q quiescent cur r ent 56 a psrr p o w er supply r ejection ratio i dldo1 =10m a ,1khz tbd db e n output noise,20- 80khz v o=3.3 v , io=20ma 100 v rms usule v dldo2 output v oltage i dldo2 =1ma -1% off 1% v i dldo2 output cur r ent 200 ma i q quiescent cur r ent 60 a psrr p o w er supply r ejection ratio i dldo2 =10m a ,1khz tbd db e n output noise,20- 80khz v o=3.3 v , io=20ma 100 v rms
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 15 symbol description conditions min typ max units usulr v dldo3 output v oltage i dldo3 =1ma -1% off 1% v i dldo3 output cur r ent 200 ma i q quiescent cur r ent 60 a psrr p o w er supply r ejection ratio i dldo3 =10m a ,1khz tbd db e n output noise,20- 80khz v o=3.3 v , io=20ma 100 v rms usuls v dldo4 output v oltage i dldo4 =1ma -1% off 1% v i dldo4 output cur r ent 100 ma i q quiescent cur r ent 60 a psrr p o w er supply r ejection ratio i dldo4 =10m a ,1khz tbd db e n output noise,20- 80khz v o=3.3 v , io=20ma 100 v rms rsulv v eldo1 output v oltage i eldo1 =1ma -1% off 1% v i eldo1 output cur r ent 400 ma i q quiescent cur r ent 55 a psrr p o w er supply r ejection ratio i eldo1 =10m a ,1khz tbd db e n output noise,20- 80khz v o=3.3 v , io=20ma 100 v rms rsule v eldo2 output v oltage i eldo2 =1ma -1% off 1% v i eldo2 output cur r ent 200 ma i q quiescent cur r ent 55 a psrr p o w er supply r ejection ratio i eldo2 =10m a ,1khz tbd db e n output noise,20- 80khz v o=3.3 v , io=20ma 100 v rms rsulr v eldo3 output v oltage i eldo3 =1ma -1% off 1% v i eldo3 output cur r ent 200 ma i q quiescent cur r ent 55 a psrr p o w er supply r ejection ratio i eldo3 =10m a ,1khz tbd db e n output noise,20- 80khz v o=3.3 v , io=20ma 100 v rms uyisul v dc5ldo output v oltage i dc5ldo =1ma -1% 1.1 1% v
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 16 symbol description condition min typ max units i dc5ldo output cur r ent 200 ma i q quiescent cur r ent 40 a psrr p o w er supply r ejection ratio i dc5ldo =10m a ,1khz tbd db e n output noise,20- 80khz v o=3.3 v , io=20ma 100 v rms suldlg v ldoio0 output v oltage i ldoio0 =1ma -1% off 1% v i ldoio0 output cur r ent 100 ma i q quiescent cur r ent 35 a psrr p o w er supply r ejection ratio i ldoio0 =10m a ,1khz tbd db e n output noise,20- 80khz v o=3.3 v , io=20ma 40 v rms suldlv v ldoio1 output v oltage i ldoio0 =1ma -1% off 1% v i ldoio1 output cur r ent 100 ma i q quiescent cur r ent 35 a psrr p o w er supply r ejection ratio i ldoio1 =10m a ,1khz tbd db e n output noise,20- 80khz v o=3.3 v , io=20ma 40 v rms uyv.4 r dc1sw in t ernal ideal r esistance pin t o pin,dcdc1, dc1sw 160 mohm y56sru r chgled in t ernal ideal r esistance vin =0.3v 2 ohm
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 17 9 o67a36o n7g b23na570 7v2 ).9 tte 54 b6/232g 67loli) b57 6t 9tdel /5oo c2 bdoo2g db a6 d 96/23 n7g am27 864an4c4a2r b36v24463p vn7 ngd4a n7g r675a63 ).9tte _ e2rn34 ia237no 96/23 c2o6/ 57vodg24 )od n7g 1l 57bda s msus 96/23 7tt e242a msusus 96/23 i7nco2 2c n9ip km2 96/23 i7nco2 lo22bn2db 2c vn7 c2 v6772va2g c2a/227 9e b57 n7g pi 6t ).9ttes).9tte vn7 nda6rna5vnooc 5g27a5tc am2 670(b3244 n7g lm63a(b3244 n7g am27 v63324b67g 324b2va52ocs msusts 9 6 / 23 7 power on source 7 be apt mln8 (y* e s 6 ci? ceec -neuu (y* gap -i?en ip 7w(~~1 )-neuu vre ien f[ymy[vkep a--cgavipk tiuv 7canr iv-v u4pac gap he gippegvet vi es6 zhepeen vhene u a act 7canr u4pac ))[i? [eecvvk 7w(~~1 gap he -i?enet ip. . 7mven -i?en ipk lb>lb apt [lf ?cc he uimv hiivet p -neuev vrp4 ue_epge . c.0.1. ( i ? en fmm zhep oi -uh>apt>hict (y* cip4en vhap es6[ymy[k tf8w gap ?nve 0 pvi syp1~t s vi pminr 7w(~~1 vi uhvti?pk ?hgh gap tuahce acc -i?en iv-v e:ge-v mbb>swb. . 8ouver -i?en>imm u pvavet ?hepeen vhe micci?p4 giptvipu iggn u p-v icva4e u vii ci?) [i?>(i?en (nivegvipv x (i?en iv-v icva4e u vii ci? te vi ienciat) fenciat (nivegvipv x ep-v icva4e u vii h4h) fenicva4e (nivegvipv) 8ee rine tevacu p gha-ven epvecc4epv (i?en 8ecegv x (uh (y* cip4en rine vhap frr[ymy[) lemacv d8vk apt uouver ?cc gv imm acc -i?en iv-v e:ge-v mbb>swb x zvh vhe aviravg -nivegvip reghapurk 7w(~~1 gap -nivegv ?hice uouver ho -neepvp4 bir-ipepvu mnir nnenuahce tara4e te vi uouver ahpinracvo.
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 18 write 1 to reg31h[3] to start the sleep and pmu will save reg10h reg12h reg13h setting at that time 9.1.4. s leep and w a k eup when the running system needs to enter sleep mode, reg31h [3] will determine whether one or several power rails should be disabled , wakeup can be triggled by either signal i a cin plug reg40[6:5] should be 1 i vbus plug reg40[3:2] should be 1 i push long time pek reg42[0] should be 1 i pek falling edge reg44[5] should be 1 i battery low power alarm reg43[1:0] should be 1 i gpio[1:0] as a general purpose input when it detects rising and falling edge reg4c[1:0] should be 1 and reg90[7:6] ref92[7:6] should be 1 i software wakeup write 1 in reg31[5] i i r q wakeup ( reg8f[7] should be 1) with all power rails resume to default voltage in default and power on timing sequence see control process under sleep and wakeup modes as below: write r e g1 0 h r e g 1 2 h r e g 1 3 h register close corresponding sleep and wait to be wakeup n wakeup y restore the power to the default output voltage.
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 19 9.1.5. .f7239 m3732 0(i l?2)?2 hc(e2c8e(d -g4mlta the pwrok in AXP223 can be used as the reset signal of application system. during AXP223 startup, pwrok outputs low level, which will then be pulled high to startup and reset the system after each output voltage reaches the regulated value . when application system works normally, AXP223 will be always monitoring the voltage and load status. if overload or under- voltage occurs, the pwrok will instantly drive low to reset the system and prevent data losses. when application system works normally drive low pwrok then AXP223 will reboot and power on timing sequence px power path m anagement (ips ? ) power input of AXP223 may come from li-battery, usb vbus input, external power acin (such as ac adapter). ips can select proper power according to external power and li-battery status . if only li-battery is available, and no external power input, li-battery is used for power input if external power is available (vbus or acin), it is preferred in power supply ; if li-battery is available, it will seamlessly switch to li-battery once external power is removed when both vbus and acin are available, acin will be applied to supply power in priority, and li-battery will be charged if acin drive capability is not enough, vbus will be enabled to achieve acin/vbus common power supply if the drive capacity is still insufficient, charge current will be reduced to zero, and battery is used for power supply host can set ips ? parameters and read the feedback by visiting internal registers in AXP223 via p2wi/rsb . 9.2.1 voltage-limit/current mode and direct mode in order not to affect the usb communication, vbus is always working under voltage-limit mode by default. in this mode, AXP223 ensures that vbus voltage remains above a configurable reference voltage vhold which can meet the usb specification. the default vhold is 4.4v, adjustable in reg30h [5:3] register . if the system has limit on current obtained from usb vbus, a current-limit mode is provided (see reg30h[1] register), with 900ma/500ma/100ma (reg30h [0]) selectable . if the system just utilizes the usb for power supply rather than communication, or the usb power adapter is utilized, AXP223 can be set to vbus direct mode by modifying register reg30h[6], and then AXP223 will give priority to the application power demand. when the drive ability of usb host is insufficient or system power consumption is large then the vbus voltage is lower than vhold, AXP223 will release irq to indicate the weak power supply ability of host vbus, which may affect usb communication, and then host software will follow up . 9.2.2 AXP223 s reaction to external power supply plugin AXP223 can automatically detect the plugin of external powers and judge whether the power is usable or not. the result will be set in corresponding registers, and irq will be released to inform the host at the same time .
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 20 the following table has listed the status bits and meanings of external power registers : register status bits description miz11qla/ indicating the presence of external acin reg00_[6] indicating whether the external acin is usable or not reg00_[5] indicating the presence of external vbus reg00_[4] indicating whether the external vbus is usable or not reg00_[3] indicating whether the vbus voltage is above vhold when used reg00_[1] indicating whether acin/vbus short circuits on pcb or not reg00_[0] indicating whether the system is triggered to startup by acin/vbus or not v the status bit of indicating whether the vbus voltage is above vhold or not when used enables the host to judge when it receives irq7(indicating weak supply ability)whether vbus is pulled low by system load input or the external power itself is below vhold, which may facilitate host software to decide either to keep on working in voltage-limit mode or switch to direct mode . 9.2.3. when to select vbus as input power n_vbusen and register reg30h[7] reg30_[2] reg8f_[4] is used to determined when shall vbus be used as power supply i reg30_[7] reg8f_[4] n_vbusen reg30h[2] yes/no 1 1 hmcb 1 uy 1 1 byt 3 %e7 1 3 hmcb uy 1 3 byt %e7 3 %e7 note: x represents any state and any value 9.2.4. low-power protection (automatic power off) xmhb g0 hbe )adse yo t 8 pashyfahm9 7bsh6ytr )ydhace( 9ar je 7e hoo hbe 7e7hef nytef m7 oysr6 b?8ou m7 dytef hbar t 8 g 0 tmdd ashyfahm9adde erhef rbsh6ytr vy6e ar6 6m7ajde add yhbef yshnsh7 e59enh tllpmdl. dbe 6eoasdh )adse yo t 8 can set in register miz03h cmhlx1/ . 9.2.5. over-voltage protection if the external power voltage exceeds 6.3v, AXP223 will release irq1/4 for indication. if the external power voltage exceeds 7v, AXP223 will automatically shutdown the system.
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 21 9.3. adaptive flash cha r ger g0 mrhecfahe7 a a6anhm)e da7b 9bafcef hy ashyfahm9adde 9yrhfyd hbe 9bafce 9e9de tmhb a jsmdhpmr 7aoehe 9dy9, 9anajde yo ashyfahm9 9bafce heffmrahmyr tmhbysh nfy9e77yf mrhef)erhmyr. dbm7 9bafcef oeahsfe7 ashyfahm9 9bafce 9sfferh 79admrc mr a99yf6ar9e tmhb hbe 7e7hef nytef 9yr7sfnhmyr a7 tedd a7 jahhefe 6ehe9hmyr hfm9,de 9bafce ar6 a9hm)ahmyr. or a66mhmyr hbe jsmdhpmr hefnefahsfe 6ehe9hmyr 9mf9smh 9ar ashyfahm9adde 6e9fea7e hbe 9bafce 9sfferh tber hbe hefnefahsfe m7 hyy bmcb yf hyy dyt. 9.3.1. adaptive charge startup the default state of the charger is enable . (it can be programmed via registers. refer to register reg33h.) when external power is plugged in, AXP223 will firstly judge whether it is chargeable. if the charger is suitable for the power, and the charge function is usable, AXP223 will automatically start the charge, and send irq to host for indication. at the same time, ghgled pin will output low level to drive external led to indicate the charging state. charge voltage/current 9.3.2. two symbolic voltages t dmzd k9bafce hafceh )ydhace. dbe t dmzd m7 g.t je 6eoasdh tbm9b 9ar je 7eh je fecm7hef pmeoef hy v miz00hlqx4/ n ( . h hbe 7afe hmfe g 0 tmdd ashyfahm9adde a6s7h hbe 9bafce hafceh )ydhace tber e5hefrad nytef )ydhace m7 dyt. tmlhkashyfahm9 fe9bafce )ydhace. tmlhktdmzdp1.3t . t mlh =automatic recharge voltage. 1 dkb 1 ad,a terh1 9.3.3. charge current the charge current is 500maor 1200ma by default, which can be set by reg33h [3:0] .
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 22 9.3.4. charge process if the battery voltage is lower than 3.0v, the charger will automatically enter the pre-charge mode, with charge current be 1/10 of the preset value. if the battery voltage is still below 3.0v 40 minutes later (adjustable, see reg34h ), charger will automatically enter the battery activate mode. refer to battery activate mode section for details . when the battery voltage reaches the 1 ad,a , the charger will switch from the constant current mode to constant voltage mode, a nd the charge current will fall when the charge current is lower than 10% or 15% (adjustable, see register reg33h ) of the preset value, a charge cycle ends, and AXP223 will release irq13 while the chgled pin will stop indicating the charging state. when the battery voltage is below t mlh again, the automatic charge will restart, and irq12 will be released. 9.3.5. battery activate mode at the entering the battery activate mode from either pre-charge mode or constant current mod(the timer expires), AXP223 will release irq10 in both cases to indicate that the battery may be damaged. in battery activate mode, the charger always inputs relatively low current to batteries. axp2 23 will exit activate mode and release irq11 only if the battery voltage has reached t mlh . g0 tmdd mr6m9ahe tbehbef hbe 9bafcef m7 mr jahhefe a9hm)ahe fy6e yf ryh mr fecm7hef miz13h . 9.3.6. chgled lhzbi? nmr m7 s7e6 hy mr6m9ahe 9bafce 7hahe ar6 tafrmrc. lhzbi? m7 uv8r 8ner ?famr yshnsh 7y a bi? 9ar je 6mfe9hde 6fm)er je a 9sfferhpdmfmh fe7m7hyf hy 7byt hbe oysf 7hahe7. dbe oyddytmrc hajde ba7 6m7ndaee6 mh7 hty ynefahmyr fy6e7 type o status performance remark charging low level not charging high resistance battery abnormal 4? 6she 3hw flicker the charger enters the battery activate mode, or the battery temperature is too high/low. over-voltage 4? 6she ghw odm9,ef external voltage input is too high type c status performance remark charging 4? 6she 3hw flicker not charging high resistance battery abnormal over-voltage 4? 6she 3hw flicker the charger enters the battery activate mode, or the battery temperature is too high/low. voltage out put is too high no battery byt be)ed uy e5hefrad nytef m7 a)amdajde.
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 23 9.3.7. battery temperature detection AXP223 can connect a temperature-sensitive resistor via the ts pin to monitor the battery temperature when the battery is charging or discharging. the diagram is shown below x in the diagram above, vth/vtl refer to the high temperature threshold and low temperature threshold, which is programmable via registers reg38h/39h/3ch/3dh respectively. vte=0.2v. the temperature-sensitive resistor is suggested to choose the ntc temperature-sensitive resistor, which is 10kohm and 1% accuracy at 25 . AXP223 will send constant current via ts pin, and the current can be set as 20ua 40ua 60ua and 80ua (see registerreg84h) to adapt to different ntc resistors. when the current goes through the temperature-sensitive resistor, a test voltage is generated, which will be measured by adc, and compared with regulated value to release corresponding irq or suspend the charge. if the resistance value of temperature-sensitive resistor is too high or too low, extra resistors can be serial or parallel connected to expand the detect extent. if the battery is free from temperature-sensitive resistor, ts pin can be linked to the ground, and in that case, AXP223 will automatically disable the battery temperature monitoring function 9.3.8 battery detection g0 tmdd ashyfahm9adde 6ehe9h hbe jahhefe nfe7er9e fe9yf6 hbe fe7sdh mr fecm7hef7 pfeoef hy miz13h( ar6 fedea7e om~30 om~3g. dbe jahhefe 6ehe9hmyr 9ar je erajde6 ar6 6m7ajde6 je hy7h. pmeoef hy fecm7hef miz0h.(
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 24 9.4. multi-power outputs the following table has listed the multi-power outputs and their functions of AXP223 output path type default voltage start-up procedure application example s drive ability ?l?l3 c:l 0.1t 3 0.1t o_8 3g11f ?l?l c:l 3.3t 3 3.3t lg: 111f ?l?l0 c:l 3.3t 3 3.3tzg: 111f ?l?lg c:l 3.3t 3 3.3t lyfe q11f ?l?l4 c:l 3.4_?l4rid 7ehhmrc 3 3.4t ??m0 111f AXP223 comes with 5 synchronous step-down dc-dcs, 14 ldos,2 switch as well as multiple timing and controlling methods. the work frequency of dc-dc is 3mhz by default, which is adjustable via registers. external small inductors and capacitors can be connected as well. in addition, 5 dc-dcs can be set in pwm mode or auto mode (automatically switchable according to the AXP223 load). see register reg80h. 9.4.1. dcdc1/2/3/4/5 ?l?l3 yshnsh )ydhace farce7 ofyf 3.q t hy 0.gt lclcxd taefae tpeicu simcu& stb ao t et goodt lclcn taefae tpeicu simcu& stb ao t et gort lclco taefae tpeicu simcu& stb goa t et xooot c im u fstcsibbu/ bi sucb&eus& dcdc5 voltage setting depends on dc5set pin voltage ?l4rid rhahs7 byt dyahmrc hmcb ?l?l4 tydhace 3.4t 3.t 3.04t dcdc output capacitor is recommended to use small esr ceramic capacitors above 10uf x7r recommend 1.5uh inductors besides, the inductor saturation current should be larger than 50% of the largest demanded current in power circuitry. mdlpb?8 b?8 0.1t 3 mdl 01f b?83 b?8 0.1 3 u_ 011f b?8 b?8 .4t 3 u_ 011f b?80 b?8 0.1t 3 u_ 11f b? 8 o81 b?8 8 8 u_ 311f b?8 o83 b?8 8 8 u_ 311f ?b?83 b?8 8 8 u_ g11f ?b?8 b?8 8 8 u_ 11f ?b?80 b?8 8 8 u_ 11f ?b?8g b?8 8 8 u_ 311f ib?83 b?8 8 8 u_ g11f ib?8 b?8 8 8 u_ 11f ib?80 b?8 8 8 u_ 11f ?l4b?8 b?8 3.3t 3 u_ 11f ?l3rx rtmh9b 8 8 u_ g11f
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 25 9.4.2. v c c- r t c tllpmdl adtae7 yr can provide uninterrupted power supply for real-time clock circuit (rtc) of application system d fm)e ajmdmhe m7 01f. 9.4.3. aldo1/2/3 b?83__0 s 7mrc a dytprym7e 6e7mcr can be used to supply power for analog circuits of application system drive ability is 011f _011f _11f . 9.4.4. ldo io0 /ldo io1 b?8 o81 _b?8 o83 s 7mrc a dytprym7e 6e7mcr hyy both output drive ability is 311f . 9.4.5. dldo1/dldo2/dldo3/dldo4 ?b?83_?b?8_?b?80_?b?8g are common low dropout linear regulators drive ability is g11f _11f _11f_311f . 9.4.6. eldo1/eldo2/eldo3/ ib?83_ib?8_ib?80_ are common low dropout linear regulators drive ability is g11f _11f _11f_ . 9.4.7. dc5ldo gytef mrnsh yo ?l4b?8 is ?l?l4 drive ability is 11f . 9.4.8. dc1sw gytef mrnsh yo ?l3rx is ?l?l3 e quivalent resistance is 3q1f8bf . 9.4.9. s o f t s ta r t all dc-dcs and ldos support soft start which can avoid the impact of dramatic current change on the input path in system boot stage. all dcdc does not require external schottky diode and resistor divider feedback circuit ,if don t need some ?l?l mr anndm9ahmyr just let the corresponding lx pin unconnected .
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 26 9.5. e-gauge v fuel gauge system m ulti ple 12bit adc of AXP223 can measuring the battery voltage and current battery charge and discharge coulometer are internal integration at the same time . based on this AXP223 integrated dual-mode fuel gauge system .under the easy mode s ave the exact of the battery parameters needs to initialize achieve high compatibility with a large number of batteries but i n precision mode optimiz ed parameters of particular battery a chieve measurement accuracy of up to 2% . e nable control and sampling rate of all adc can be set visa register reg84h s ample results are stored in the corresponding register see the adc data description of register . decide b y register reg00h[2] . channel 000h step fffh battery voltage 0mv 1.1mv 4.5045v bat discharge current 0ma 1ma 4.095a bat charge current 0ma 1ma 4.095a internal temperature -267.7 0.1 165.8 ts pin input 0mv 0.8mv 3.276v 9.6. multi-function pin description gpio[1:0] can be defined as gpio[1:0],or ldo, etc. please refer to reg90h-96h instruction for details . chgled features charge state indication, over-temperature/over-voltage warning, and motor-drive if reg32[2]=0 the pin driveability is 100ma connect micro vibration motor to 3.3v power serial links to current limiting resistor v ibration motor can be driven directly . if reg32[2]=1 the pin s tate is charg ing over-temperature and over-voltage warning function indicator . 9.7. timer AXP223 features a internal timer, whose values can be programmed via register reg8ah[6:0]. the minimum time step of timer is minute timer will be set in reg8ah[7] after timeout .
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 27 9.8 interrupt mechanism hy7h 9ar )m7mh g0 fecm7hef7 )ma hbe gxo_mrc mrhefoa9e ar6 hbe bmcbe7h fahe 9ar fea9b vhw. or a66mhmyr fsdhm fea6 ar6 tfmhe ynefahmyr m7 7snnyfhe6 . xber 9efhamr e)erh7 y99sf g0 tmdd mroyff hy7h je nsddmrc 6ytr hbe om~ mrheffsnh fe9barm7f ar6 hbe mrheffsnh 7hahe tmdd je fe7ef)e6 mr mrheffsnh 7hahe fecm7hef7 pree fecm7hef7 mizgsh mizgh mizgh mizgch ar6 mizglh(. dbe mrheffsnh 9ar je 9deafe6 je tfmhmrc 3 hy 9yffe7nyr6mrc 7hahe fecm7hef jmh. xber hbefe m7 ry mrheffsnh om~ yshnsh tmdd je nsdde6 bmcb p43 fe7m7har9e bmcbef hbfyscb hbe e5hefrad(. ia9b mrheffsnh 9ar je fa7,e6 )ma mrheffsnh 9yrhfyd fecm7hef7 pmeoef hy fecm7hef7 mizg1h mizg3h mizgh mizg0h ar6 mizggh(. reg irq description reg irq description reg 48_[7] i r q1 acin over voltage reg gcqla/ reg 48_ [6] i r q2 acin plug in reg gcq lq/ reg gsq l4/ i r q3 acin removal reg gcq l4/ reg gsq lg/ i r q4 vbus over voltage reg gcq lg/ reg gsq l0/ i r q5 vbus plug in reg gcq l0/ reg gsq l/ i r q6 vbus removal reg gcq l/ reg gsq l3/ i r q7 vbus voltage lower than v hold reg gcq l3/ i r q19 low power level1 reg gsq l1/ reserved reg gcq l1/ i r q20 low power level2 reg gqla/ i r q8 battery plugin reg glqla/ i r q21 timer done reg gq lq/ i r q9 battery removal reg glq lq/ i r q22 pek rising edge reg gq l4/ i r q10 enter battery activate mode reg glq l4/ i r q23 pek falling edge reg gq lg/ i r q11 exit battery activate mode reg glq lg/ reg gq l0/ i r q12 charging reg glq l0/ reg gq l/ i r q13 charge done reg glq l/ reserved reg gq l3/ i r q14 battery temp too high reg glq l3/ i r q24 gpio1 edge trigger reg gq l1/ i r q15 battery temp too low reg glq l1/ om~ 5 gpio0 edge trigge r reg gq la/ i r q16 die temp too high reg gq lq/ reserved reg gq l4/ reserved reg gq lg/ reserved reg gq l0/ reserved reg gq l/ reserved reg gq l3/ i r q17 pek short-press reg gq l1/ i r q18 pek long-press
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 28 10 e2054a23 uasus e2054a23 uasusus 96/23 o67a36o )gg3244 e2054a23 i24v35ba567 e i2tndoa nod2 aa 96/23 4anad4 32054a23 e au 96/23 r6g2 vmn302 4ana2 32054a23 e aw(ay inan cdtt23 32054a23 e aa8 ua ioioutewh)iutiohi 27nco2 n7g g54nco2 v67a36o 32054a23 e y8 ut iiuteiiutewioul 27nco2 n7g g54nco2 v67a36o 32054a23 e aa8 ue )ie yy v67a36o 32054a23 e au8 uh iiu 6oan02 42aa570 32054a23 e aa8 ug iit 6oan02 42aa570 32054a23 e aa8 us iie 6oan02 42aa570 32054a23 e aa8 ur iiw 6oan02 42aa570 32054a23 e aa8 um iiu 6oan02 42aa570 32054a23 e aa8 u) iit 6oan02 42aa570 32054a23 e aa8 u iie 6oan02 42aa570 32054a23 e aa8 uo iohi 6oan02 42aa570 32054a23 e aa8 tu ioiou 6oan02 42aa570 32054a23 e aa8 tt ioiot 6oan02 42aa570 32054a23 e aa8 te ioioe 6oan02 42aa570 32054a23 e aa8 tw ioiow 6oan02 42aa570 32054a23 e aa8 th ioioh 6oan02 42aa570 32054a23 e aa8 ts ioiote 6oan02 3nrb bn3nr2a23 42aa570 32054a23 e aa8 tr )iu 6oan02 42aa570 32054a23 e aa8 tm )it 6oan02 42aa570 32054a23 e aa8 t) )ie 6oan02 42aa570 32054a23 e aa8 ea 1l(d9lk vmn772o 42aa570 32054a23 e ga8 eu n2db v67a36o n7g 1yy 4mdag6/7 6oan02 42aa570 32054a23 e ae8 et lmdag6/7 cnaa23c g2a2va567 o8pii v67a36o 32054a23 e we8 ee omn302 v67a36o 32054a23 u e og8 ew omn302 v67a36o 32054a23 t e wh8 eh omn302 v67a36o 32054a23 e e ai8 eg 9i bn3nr2a23 v67a36o 32054a23 e hi8 es ioio v6723a23 /63 t32d27vc 42aa570 32054a23 e ar8 er naa23c vmn302 d7g23(a2rb23nad32 /n37570 42aa570 32054a23 e )h8
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 29 address register description r/w default value 39 battery charge over-temperature warning setting register r/w 1fh 3c battery discharge under-temperature warning setting register r/w fch 3d battery discharge over-temperature warning setting register r/w 16h 80 dcdc work mode setting register r/w 80h 82 adc enable setting register1 r/w e0h 84 adc sample rate setting ts pin control register r/w 32h 85 ts adc sample rate setting register r/w 00h 8a timer control register r/w 00h 8c/8d pwren control register r/w 00h 8f over-temperature shutdown control register r/w 01h 10.1.2. gpio control address register description r/w default value 90 gpio0 control register r/w 07h 91 gpio0 ldo output voltage setting register r/w 1fh 92 gpio1 control register r/w 07h 93 gpio1 ldo mode output voltage setting control register r/w 1fh 94 gpio[1:0] signal status register r/w 00h 97 gpio[1:0] pull-down control register r/w 00h 10.1.3. interrupt control address register description r/w default value 40 irq enable control register 1 r/w d8h 41 irq enable control register 2 r/w ffh 42 irq enable control register 3 r/w 03h 43 irq enable control register 4 r/w 03h 44 irq enable control register 5 r/w 00h 48 irq status register 1 r/w 00h 49 irq status register 2 r/w 00h 4a irq status register 3 r/w 00h 4b irq status register 4 r/w 00h 4c irq status register 5 r/w 00h 10.1.4. adc data address register description r/w 56 a xp223 internal temperature monitoring adc data high 8 bits r 57 AXP223 internal temperature monitoring adc data low 4 bits r 58 ts input adc data high 8 bits default monitoring battery temperature r 59 ts input adc data low 4 bits default monitoring battery temperature r 78 battery voltage high 8 bits r
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 30 address register description r/w 79 battery voltage low 4 bits r 7a battery charge current high 8 bits r 7b battery charge current low 4 bits r 7c battery discharge current high 8 bits r 7d battery discharge current low 5 bits r b8 fuel guage control register r/w c0h b9 fuel guage result register r 64h e0 total capacity of battery bit[14:8] r/w 00h e1 total capacity of battery bit[7:0] r/w 00h e6 low battery alarm setting register r/w a0h e8h s et the interval update time for fuel gauge percentage r/w 00h e9h fuel gauge calibration interval setting r/w 00h ech coulomb counter percentage of electricity calibration points setting r/w 00h note the total capacity of battery unit is 3.g4qfh 10.2. register description 1 0.2.1. reg 00h: power input status
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 31 10.2.2. reg 01h: power working mode and charge status indication pe2 u37b8e)2ec( mw4 7 indicating whether axp2 23 is over-temperature 0: not over-temperature 1: over-temperature r 6 charge indication 0:not charge or charge finished 1: in charging r 5 battery existence indication 0:no battery connected to axp2 23 1:battery already connected to axp2 23 r 4 reserved and unchangeable r 3 indicating whether the battery enters the activate mode 0: not enter the activate mode 1: already entered the activate mode r 2-0 reserved and unchangeable r 10.2.3. reg 04-0fh: data cache note: as long as one of the external powers, batteries or backup batteries exists, this data will be reserved and free from the startup and shutdown influence . 10.2.4. reg 10h: dcdc1/2/3/4/5&aldo1/2&dc5ldo power output control default value : ff h bit description r/w default value 7 aldo2 enable and disable control 0: disable 1: enable rw 1 6 aldo1 enable and disable control rw 1 5 dcdc5 enable and disable control rw 1 4 dcdc 4 enable and disable control rw 1 3 dcdc 3 enable and disable control rw 1 2 dcdc 2 enable and disable control rw 1 1 dcdc 1 enable and disable control rw 1 0 dcdc 0 enable and disable control rw 1
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 32 10.2.5. reg 12h: power output control default value x11h bit description r/w default value a ?l3rx erajde ar6 6m7ajde 9yrhfyd 1x 6m7ajde g umipu m a llpd enable and disable control mx 1 4 ?b?80 enable and disable control mx 1 g ?b?8 enable and disable control mx 1 0 ?b?83 enable and disable control mx 1 ib?80 enable and disable control mx 1 3 ib?8 enable and disable control mx 1 1 ib?83 enable and disable control mx 1 10.2.6. reg 13h: power output control default value xs3h bit description r/w default value a b?80 enable and disable control 1x 6m7ajde g umipu m g la reserved and unchangeable 10.2.7. reg 15h:dldo1 output voltage setting default value x11h bit description r/w default value ap4 reserved and unchangeable 4 ?b?83 output voltage setting cmhg 1.ap0.0t311ft_7hen mx 1 0 ?b?83 output voltage setting cmh0 mx 1 ?b?83 output voltage setting cmh mx 1 3 ?b?83 output voltage setting cmh3 mx 1 1 ?b?83 output voltage setting cmh1 mx 1 10.2.8. reg 16h:dldo2 output voltage setting default value x11h bit description r/w default value ap4 reserved and unchangeable 4 ?b?8 output voltage setting cmhg 1.ap0.0t311ft_7hen mx 0 0 ?b?8 output voltage setting cmh0 mx 0 ?b?8 output voltage setting cmh mx 0 3 ?b?8 output voltage setting cmh3 mx 0 1 ?b?8 output voltage setting cmh1 mx 1
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 33 10.2.9. reg 17h:dldo3 output voltage setting default value x11h 10.2.10. reg 18h:dldo4 output voltage setting default value x11h bit description r/w default value ap4 reserved and unchangeable g ?b?8g output voltage setting cmhg 1.ap0.0t311ft_7hen mx 1 0 ?b?8g output voltage setting cmh0 mx 1 ?b?8g output voltage setting cmh mx 1 3 ?b?8g output voltage setting cmh3 mx 1 1 ?b?8g output voltage setting cmh1 mx 1 10.2.11. reg 19h:eldo1 output voltage setting default value x11h bit description r/w default value ap4 reserved and unchangeable g ib?83 output voltage setting cmhg 1.ap0.0t311ft_7hen mx 1 0 ib?83 output voltage setting cmh0 mx 1 ib?83 output voltage setting cmh mx 1 3 ib?83 output voltage setting cmh3 mx 1 1 ib?83 output voltage setting cmh1 mx 1 bit description r/w default value ap4 reserved and unchangeable g ?b?80 yshnsh )ydhace 7ehhmrc cmhg 1.ap0.0t311ft_7hen mx 1 0 ?b?80 output voltage setting cmh0 mx 1 ?b?80 output voltage setting cmh mx 1 3 ?b?80 output voltage setting cmh3 mx 1 1 ?b?80 output voltage setting cmh1 mx 1
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 34 10.2.12. reg 1ah:eldo2 output voltage setting default value x11h bit description r/w default value ap4 reserved and unchangeable g ib?8 output voltage setting cmhg 1.ap0.0t311ft_7hen mx 1 0 ib?8 output voltage setting cmh0 mx 1 ib?8 output voltage setting cmh mx 1 3 ib?8 output voltage setting cmh3 mx 1 1 ib?8 output voltage setting cmh1 mx 1 10.2.13. reg 1bh:eldo3 output voltage setting default value x11h bit description r/w default value ap4 reserved and unchangeable g ib?80 output voltage setting cmhg 1.ap0.0t311ft_7hen mx 1 0 ib?80 output voltage setting cmh0 mx 1 ib?80 output voltage setting cmh mx 1 3 ib?80 output voltage setting cmh3 mx 1 1 ib?80 output voltage setting cmh1 mx 1 10.2.14. reg 1ch:dc5ldo output voltage setting default value x1gh bit description r/w default value ap0 reserved and unchangeable ?l4b?8 output voltage setting cmh 1.ap3.gt311ft_7hen mx 3 3 ?l4b?8 output voltage setting cmh3 mx 1 1 ?l4b?8 output voltage setting cmh1 mx 1 10.2.15. reg 21h:dcdc1 output voltage setting default value x1ih bit description r/w default value ap4 reserved and unchangeable 4 ?l?l3 output voltage setting cmhg 3.qp0.gt 311ft_7hen mx 0 3 ?l?l3 output voltage setting cmh0 mx 1 2 ?l?l3 output voltage setting cmh mx 1 1 ?l?l3 output voltage setting cmh3 mx 1 0 ?l?l3 output voltage setting cmh1 mx 0
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 35 10.2.16. reg 22h:dcdc2 output voltage setting default value x3h bit description r/w default value ap q reserved and unchangeable 4 ?l?l output voltage setting cmh 4 1.qp3.4gt 1ft_7hen mx 1 g ?l?l output voltage setting cmh g mx 3 0 ?l?l output voltage setting cmh 0 mx 3 ?l?l output voltage setting cmh mx 1 3 ?l?l output voltage setting cmh 3 mx 1 1 ?l?l output voltage setting cmh 1 mx 3 10.2.17. reg 23h:dcdc3 output voltage setting default value x3h bit description r/w default value apq reserved and unchangeable 4 ?l?l0 output voltage setting cmh4 1.qp3.sqt 1ft_7hen mx 1 g ?l?l0 output voltage setting cmhg mx 3 0 ?l?l0 output voltage setting cmh0 mx 3 ?l?l0 output voltage setting cmh mx 1 3 ?l?l0 output voltage setting cmh3 mx 1 1 ?l?l0 output voltage setting cmh1 mx 3 10.2.18. reg 24h:dcdc4 o utput voltage setting default value x3h bit description r/w default value apq reserved and unchangeable 4 ?l?l g output voltage setting cmh4 1.qp3.sqt 1ft_7hen mx 1 g ?l?l g output voltage setting cmhg mx 3 0 ?l?l g output voltage setting cmh0 mx 3 ?l?l g output voltage setting cmh mx 1 3 ?l?l g output voltage setting cmh3 mx 1 1 ?l?l g output voltage setting cmh1 mx 3
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 36 10.2.19. reg 25h:dcdc5 o utput voltage setting default value x1h bit description r/w default value ap 4 reserved and unchangeable g ?l?l 4 output voltage setting cmhg 3.1p.44t 41ft_7hen mx 1 0 ?l?l 4 output voltage setting cmh0 mx 3 ?l?l 4 output voltage setting cmh mx 1 3 ?l?l 4 output voltage setting cmh3 mx 3 1 ?l?l 4 output voltage setting cmh1 mx 1 uyhex dbe 6eoasdh )ydhace 6ener67 yr dc5set 1 0.2.20. reg 27h:dcdc2/3 dynamic voltage scaling parameter setting default value x11h bit description r/w default value ap g reserved and unchangeable 0 ?l? l 0 tml iucbouz l8udm8b 1x erajde g /b&ipu m a x lcl c x tmc gy cpkmp a umipu g /b&ipu m a g lclcn tmc tpeicu sb&bmc &ptfu vtmestp a xobtgooxoa&gobta& g xobtngoxoaa&aorbta& m a a lclcx tmc tpeicu sb&bmc &ptfu vtmestp a xobtgooxoa&gobta& g xobtngoxoaa&aorbta& m a
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 37 10.2.21. reg 28h:aldo1 o utput voltage setting default value x3ah bit description r/w default value ap4 reserved and unchangeabl e g b?83 output voltage setting cmhg 1.ap0.0t311ft_7hen mx 3 0 b?83 output voltage setting cmh0 mx 1 b?83 output voltage setting cmh mx 3 3 b?83 output voltage setting cmh 3 mx 3 1 b?83 output voltage setting cmh1 mx 3 10.2.22. reg 29h:aldo2 o utput voltage setting default value x3h bit description r/w default value ap4 reserved and unchangeabl e g b?8 output voltage setting cmhg 1.ap0.0t311ft_7hen mx 3 0 b?8 output voltage setting cmh0 mx 1 b?8 output voltage setting cmh mx 1 3 b?8 output voltage setting cmh3 mx 3 1 b?8 output voltage setting cmh1 mx 1 10.2.23. reg 2ah:aldo3 o utput voltage setting default value x3ah bit description r/w default value 7-5 reserved and unchangeabl e 4 b?80 output voltage setting cmhg 1.ap0.0t311ft_7hen mx 3 3 b?80 output voltage setting cmh0 mx 1 2 b?80 output voltage setting cmh mx 3 1 b?80 output voltage setting cmh3 mx 3 0 b?80 output voltage setting cmh1 mx 3
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 38 10.2.24 reg 30h:vbus-ipsout power path management default value xq1h bit description r/w default value a the vbus-ipsout path select control signal when vbus is usable 0: whether to enable the path is decided by n_vbusen pin 1:vbus-ipsout can be enabled regardless of the n_vbusen status rw 0 1uu 1 bsc_ v0w9ri3twpnp9 s049l0w ei 409 wpnp9 9v3 v0w9ri3 g pbbbe eu tpeicu m g o t pl setting cmh 111x g.1t 113x g.3t 131x g.t mx 3 g t h8b? setting cmh 3 133x g.0t 311x g.gt 313x g.4t mx 1 0 t h8b? setting cmh 1 31x g.qt 333x g.at mx 1 ?motitc:r a7 hbe yshnsh 7hahe 9yrhfyd tber yshnsh 1x dyt de)ed ysh nsh 3xogr ysh mx 1 3p1 tc:r 9sfferhpdmfmh 7ehhmrc 11x11f & 13x411f& 31x311f& 33xryh dmfmh mx 11
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 39 10.2.25. reg 31h: wakeup control and v off power off voltage setting default value x10h bit description r/w default value a if pwrok is pulled low in the wake process 0:no 1: yes rw 0 soft reboot control, write 1 in this bit then pmu will restart, and bit is automatically cleared mx 1 4 software wake control , write 1 in bit then each output will resume, and bit is automatically cleared mx 1 g when enable wakeup function ,if irq enable wakeup, if masked in wakeup process 0 irq enable wakeup,and masked in wakeup process 1 irq working ,but disable wakeup dc e e wakeup function enable setting in sleep mode 0 disable 1 enable this bit will be automatically cleared to 0 after writing so 1 should be rewritten whenever enters the sleep mode. dc e w 1 szz set cmh 111p.qt 113p.at 131p.st 133p mx 1 3 t 8 set cmh 3 .t 311p0.1t 313p0.3t mx 3 1 t 8 set cmh 1 331p0.t 333p0.0t mx 3 10.2.26. reg 32h: shutdown setting, battery detection and chgled pin control default value xg0h bit description r/w default value a shutdown control writing 1 to this bit will disable the AXP223 output,expect rtc and charging module rw 0 ur993l[ n04p90lp4i m54s9p04 g399p4i :p9i ei hpgr:w3 g umipu m g old chgled pin function setting 00: high resistance 01: 25% 0.5hz flicker 10: 25% 2hz flicker 11: low level output mx 11 0 chgled pin control setting 0: controlled by register reg 32h[5:4] 1: controlled by charging mx 1 output disable timing control 0: disable at the same time 1: contrary to the startup timing mx 1 3p1 pwrok start delay time compare last power output 00: 8ms 01: 16ms 10: 32ms 11: 64ms mx 33
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 40 10.2.27. reg 33h: charging control 1 default value xlqh bit description r/w default value a charging enable control bit,include internal and external channel 0: disable 1:enable rw 1 ty kvrlip4i 9rli39tv0w9ri3 g399p4i eeinrh1 agdoxxt gadoxt ggdoxdt m ga d charging end-current setting 0: end when the charge current is lower than 10% of the set value 1: end when the charge current is lower than 15% of the set value mx 1 0p1 charge current setting 1111x011f 1113xg41f 1131xq11f 1133xa41f 1311x11f 1313x3141f 1331x311f 1333x3041f 3111x3411f 3113x3q41f 3131x3s11f 3133x341f 3311x311f mx 1331 10.2.28. reg 34h: charging control 2 default value inyb bit description r/w default value a pre-charge timeout setting cmh3 11x g1 fmr 13x 41fmr mx 1 q pre-charge timeout setting cmh1 31x q1fmr 33x a1fmr mx 3 4 if close charg output after charge finsih 1 close 3 open mx 1 g lhzbi? fy6e 7ede9hmyr 1 k.fu g k.fu m a n mu&usu/ im/ amvimcuipu x if charging constant follows charging current when value changed 1 not follow 3 follow mx 3 3 constant-current mode timeout setting cmh3 11x qhysf7 13x shysf7 mx 1 1 constant-current mode timeout setting cmh1 31x 31hysf7 33x 3hysf7 mx 3 note type _c please refer to "adaptive flash charger" instruction for details.
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 41 10.2.29. reg 35h: charging control 3 default value x1ih bit description r/w default value a pg me7ef)e6 ar6 sr9barceajde 0p1 limit charging loop current setting 1111x011f aaagdoab aagaaab aaggoab agaaaab agaggaoab aggagxaab aggggnoab gaaagoaab gaaggoab gagagraab gagggoab ggaaxgaab ggagxxoab ggga xdaab gggg xooab m ggga 10.2.30. reg 36h:pek key parameters setting default value x4h bit description r/w default value a startup time setting cmh3 11x 3sfr 13x 3r mx 1 q startup time setting cmh1 31x r 33x 0r. mx 3 4 long-press time setting cmh3 11x 3r 13x 3.4r mx 1 g long-press time setting cmh1 31x r 33x .4r. mx 3 0 automatic shutdown setting when the key press-time exceeds the shutdown time 0: disable 1: enable mx 3 automatic restart after automatic shutdown when the key press-time exceeds the shutdown time 0: disable 1: enable mx 1 3 shutdown time setting cmh3 11x gr 13x qr mx 1 1 shutdown time setting cmh1 31x sr 33x 31r mx 3
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 42 10.2.31. reg 37h:dcdc working frequency setting default value x1sh 10.2.32. reg 38h:v l tf-cha r ge battery charge under-temperature threshold setting default value x4h bit description r/w default value 7-0 battery under-temperature threshold setting when the battery is c harging v vk31h um so vtssu&ftm/bmc tpeicu b& xoggxt vtssu&ftm/bmc tpeicu simcu& stb atdnoxdt m o t klviscu s ga aoaaart 10.2.33. reg 39h:vhtf-cha r ge battery charge over-temperature threshold setting default value x3h bit description r/w default value ap1 the battery over-temperature threshold setting when the battery is charging n uk31h um g eu vtssu&ftm/bmc tpeicu b& aont vtssu&ftm/bmc tpeicu simcu& stb atdnoxdt m g t klviscu ga aoaaart bit description r/w default value 7 dcdc and pwm charger spread spectrum function setting 0: disable 1:enable 1 q dcdc and pwm charger spread spectrum frequency setting 0: 50khz 1:100khz 1 4 me7ef)e6 ar6 sr9barceajde 1 g dcdc 2&2 poly-phase function setting 0:disable 1:enable 1 0 dcdc enable/disable frequency setting bit 3 each level changes by 5% default value1.3mhz dc h w dcdc enable/disable frequency setting bit 2 2 mx 1 3 dcdc enable/disable frequency setting bit 1 mx 1 1 dcdc enable/disable frequency setting bit 0 mx 1
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 43 10.2.34. reg 3ch:v l tf-discha r ge battery discharging under-temperature threshold setting default value xlh bit description r/w default value ap1 the battery over-temperature threshold setting when the battery is discharging v vk31h um sc vtssu&ftm/bmc tpeicu b& noxxt vtssu&ftm/bmc tpeicu simcu& stb atdnoxdt m c t kl/b&viscu s ga aoaaart 10.2.35. reg 3dh:vhtf-discha r ge battery discharging over-temperature threshold setting default value x3qh bit description r/w default value ap1 the battery over-temperature threshold setting when the battery is discharging u uk31h um g vtssu&ftm/bmc tpeicu b& aoxrxt vtssu&ftm/bmc tpeicu simcu& stb atdnoxdt m g t kl/b&viscu ga aoaaart 10.2.36. reg 80h:dcdc working mode selection default value xs1h bit description r/w default value 7-5 reserved and unchangeable g dcdc 4 work mode control 0:pfm/pwm automatic switching 1: fixed pwm mx 1 0 dcdc 3 work mode control mx 1 dcdc2 work mode control mx 1 3 dcdc 1 work mode control mx 1 1 dcdc 0 work mode control mx 1
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 44 10.2.37. reg 82h:adc enable default value xi1h bit description r/w default value a battery voltage adc enable 0: disable 1: enable dc h battery current adc enable mx 3 4 internal temperature adc enable mx 3 gp3 reserved and unchangeable 1 dr nmr ?l osr9hmyr erajde 0: disable 1: enable dc e 10.2.38. reg 84h:adc sample rate setting and ts pin control default value x0h bit description r/w default value a ?l sample rate setting cmh 3 31 j r sample rate is 311 11 g11 s11hw mx 1 q ?l sample rate setting cmh 1 mx 1 4pg dr pin output current setting: 11x1s 13xg1s 31xq1s 33xs1s mx 33 0 reserved and unchangeable dr nmr osr9hmyr 7ede9hmyr 1x jahhefe hefnefahsfe fyrmhyfmrc osr9hmyr g uweusmip bm/ufum/ume lc m a gla kh fbm vassume taefae buet/ &ueebmc aa /b&ipu ag vassume taefae um viscbmc ga bmfae um eu lc b& &ibfpbmc su/avbmc eu ftus vtm&abfebtm gg ipi.& umipu m g m a
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 45 10.2.39. reg 85h:ts adc sample rate setting default value x11h bit description r/w default value a dr ?l sample rate setting 3 31 j r sample rate is 311 11 g11 s11hw mx 1 q dr ?l sample rate setting 1 mx 1 4p1 reserved and unchangeable 10.2.40. reg 8ah: timer control default value x11h bit description r/w default value a the timer is timeout write 1 to clear the status. mx 1 6-0 set the time unit: minute write full 0 to shutdown the timer. rw 0000000 10.2.41. reg 8ch: p wren control setting 1 default value x11h bit description r/w default value 7 dcdc1 whether control by pwren 0:no 1:yes mx 1 q dcdc 2 whether control by pwren mx 1 4 dcdc 3 whether control by pwren mx 1 g dcdc 4 whether control by pwren mx 1 0 dcdc 5 whether control by pwren mx 1 aldo1 whether control by pwren mx 1 3 aldo2 whether control by pwren mx 1 1 aldo3 whether control by pwren mx 1
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 46 10.2.42. reg 8dh: p wren control setting 2 default value x11h bit description r/w default value 7 dlod 1 whether control by pwren 0:no 1:yes mx 1 q dlod2 whether control by pwren mx 1 4 dlod3 whether control by pwren mx 1 g dlod4 whether control by pwren mx 1 0 elod1 whether control by pwren mx 1 eldo2 whether control by pwren mx 1 3 eldo3 whether control by pwren mx 1 1 dc5ldo whether control by pwren mx 1
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 47 10.2.43. reg 8fh: function setting, over-temperature shutdown, etc. default value x13h bit description r/w default value 7 irq pin trigger boot or wake-up settings 0:disable 1:enable mx 1 q acin/vbus in-shot function setting 0:automatic detection 1:control by reg8f_[5] mx 1 4 acin/vbus set by in-short 0:on not in-short status 1: on in-short status mx 1 g n_vbusen pin function control 0:output pin,be drivebus function( output to drive external otg boost module) 1:input pin,be n_vbusen function(input control vbus path) mx 1 0 reset ic when press longtime key 16seconds 0:no reset 1:reset dc e 2 AXP223 internal over-temperature shutdown setting 0: not shutdown 1: shutdown mx 1 3 p1 reserved and unchangeable dc e h
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 48 10.2.44. reg 90h:gpio0 function setting default value x1ah 10.2.45. reg 91h:gpio0 be ldo mode and output high level setting default value x3h bit description r/w default value ap4 reserved and unchangeable g zgo81 b?8 output voltage setting cmhg 1.ap0.0t311ft_7hen mx 3 0 zgo81 b?8 output voltage setting cmh0 mx 3 zgo81 b?8 output voltage setting cmh mx 3 3 zgo81 b?8 output voltage setting cmh3 mx 3 1 zgo81 b?8 output voltage setting cmh1 mx 3 bit description r/w default value 7 gpio0 be input function ,rising edge irq or wakeup function 0 disable 1 enable mx 1 q gpio0 be input function ,falling edge irq or wakeup function 0 disable 1 enable mx 1 4 p0 reserved and unchangeable 2 gpio0 pin function setting bit 2 000: output low 001: output high 010: general input function 011: enalbe low noise ldo 100: disalbe low noise ldo 101-111:floating mx 3 3 gpio0 pin function setting bit 1 dc h e gpio0 pin function setting bit 0 dc h
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 49 10.2.46. reg 92h:gpio1 function setting default value x1ah 10.2.47. reg 93h:gpio1 be ldo mode and output high level setting default value x3h bit description r/w default value ap4 output voltage setting g zgo83 b?8 output voltage setting cmhg 1.ap0.0t311ft_7hen mx 3 0 zgo83 b?8 output voltage setting cmh0 mx 3 zgo83 b?8 output voltage setting cmh mx 3 3 zgo83 b?8 output voltage setting cmh3 mx 3 1 zgo83 b?8 output voltage setting cmh1 mx 3 10.2.48. reg 94h:gpio[1:0] in put signal status monitoring default value x11h bit description r/w default value ap 3 zgo83 input status 0: input low level 1: input high level m 0 1 zgo81 input status m 0 bit description r/w default value 7 gpio0 be input function ,rising edge irq or wakeup function 0 disable 1 enable mx 1 q gpio0 be input function ,falling edge irq or wakeup function 0 disable 1 enable mx 1 4 p0 reserved and unchangeable 2 gpio0 pin function setting bit 2 000: output low 001: output high 010: general input function 011: enable low noise ldo 100: disable low noise ldo 101-111:floating mx 3 3 gpio0 pin function setting bit 1 dc h e gpio0 pin function setting bit 0 dc h
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 50 10.2.49. reg 97h:gpio[1:0] pull-down setting for input default value x11h bit description r/w default value ap reserved and unchangeable 3 zgo83 pull-down resistor control 1x6m7ajde 3xerajde mx 1 1 zgo81 pull-down resistor control mx 1 10.2.50. reg 40h:i r q enable 1 default value x?sh bit description r/w default value a lou y)efp)ydhace om~ erajde mx 3 q lou 9yrre9he6 om~ erajde mx 3 4 lou fefy)e6 om~ erajde mx 1 g tc:r y)efp)ydhace om~ erajde mx 3 0 tc:r 9yrre9he6 om~ erajde mx 3 tc:r fefy)e6 om~ erajde mx 1 3 tc:r m7 a)amdajde jsh dytef hbar t h8b? om~ erajde mx 1 1 reserved and unchangeable mx 1 10.2.51. reg 41h:i r q enable 2 default value xh 10.2.52. reg 42h:i r q enable 3 default value x10h bit description r/w default value a g0 mrhefrad y)efphefnefahsfe om~ erajde mx 1 qp reserved and unchangeable 3 pek short press, irq enable mx 3 1 pek long press, irq enable mx 3 bit description r/w default value a battery connected, irq enable mx 3 q battery removed, irq enable mx 3 4 battery activate mode, irq enable mx 3 g exit battery activate mode, irq enable mx 3 0 be charging, irq enable mx 3 charge finished, irq enable mx 3 3 battery over-temperature, irq enable mx 3 1 battery low-temperature, irq enable mx 3
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 51 10.2.53. reg 43h:i r q enable 4 default value x10h bit description r/w default value ap reserved and unchangeable 3 battery level reaches the alarm threshold 3 om~ enable tips mx 3 1 battery level reaches the alarm threshold om~ enable shut down mx 3 10.2.54. reg 44h:i r q enable 5 default value x11h bit description r/w default value a timer timeout om~ erajde mx 1 q gi rising edge, irq enable mx 1 4 gi falling edge, irq enable mx 1 gp reserved and unchangeable 3 zgo83 input edge trigger, irq enable mx 1 1 zgo81 input edge trigger, irq enable mx 1 10.2.55. reg 48h:i r q status 1 bit description r/w default value a lou y)efp)ydhace om~ 7hahs7 mx 1 q lou 9yrre9he6 om~ 7hahs7 mx 1 4 lou fefy)e6 om~ 7hahs7 mx 1 g tc:r y)efp)ydhace om~ 7hahs7 mx 1 0 tc:r 9yrre9he6 om~ 7hahs7 mx 1 tc:r fefy)e6 om~ 7hahs7 mx 1 3 tc:r m7 a)amdajde jsh dytef hbar t h8b? om~ 7hahs7 mx 1 1 reserved and unchangeable mx 1 10.2.56. reg 49h:i r q s tatus 2 bit description r/w default value a battery connected om~ 7hahs7 mx 1 q battery removed om~ 7hahs7 mx 1 4 battery activate mode om~ 7hahs7 mx 1 g exit battery activate mode om~ 7hahs7 mx 1 0 be charging om~ 7hahs7 mx 1 charge finished om~ 7hahs7 mx 1 3 battery over-temperature om~ 7hahs7 mx 1 1 battery low-temperature om~ 7hahs7 mx 1
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 52 10.2.57. reg 4ah:i r q s tatus 3 bit description r/w default value a g0 mrhefrad y)efphefnefahsfe om~ 7hahs7 mx 1 qp me7ef)e6 ar6 sr9barceajde 3 gi 7byfh nfe77 om~ 7hahs7 mx 1 1 gi dyrc nfe77 om~ 7hahs7 mx 1 10.2.58. reg 4bh:i r q status 4 bit description r/w default value ap reserved and unchangeable 3 battery level reaches the alarm threshold irq 1 status mx 1 1 battery level reaches the alarm threshold irq 2 status mx 1 10.2.59. reg 4ch:i r q status 5 bit description r/w default value a timer timeout irq status mx 1 q gi fm7mrc e6ce om~ 7hahs7 mx 1 4 gi oaddmrc e6ce om~ 7hahs7 mx 1 gp reserved and unchangeable 3 zgo83 mrnsh e6ce hfmccef om~ 7hahs7 mx 1 1 zgo81 mrnsh e6ce hfmccef om~ 7hahs7 mx 1 note: writing 1 to all irq status register bits will clear corresponding status . 10.2.60. reg b8h: fuel gauge control default value l1h bit description r/w default value a fuel gauge enable 0:disable 1:enable mx 3 q coulomb counter enable 0:disable 1:enable mx 3 4 total capacity of battery calibration function enable 0:disable 1:enable mx 1 g total capacity of battery calibration function status 0: calibration 1: no calibration mx 1 0p 1 reserved and unchangeable mx 1
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 53 10.2.61. reg b9h: indicate battery level default value nb 10.2.62. reg e0h: b attery capacity setting 1 default value 11h uyhe x jahhefe 9ana9mhe k tadse k 3.g4qfb bit description r/w default value a battery is calculated correctly 1 no 3 yes m 1 qp1 indicate battery level 1?2311? m qg bit description r/w default value a battery capacity is configured 1 no 3 yes m x 1 qp1 battery capacity setting jmhl3gxs/ 1?2311? m x 1
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 54 1 0.2.63. reg e1h: b attery capacity setting 2 default value : eeb 10.2.64. reg e6h: low battery power alarm threshold settings ?eoasdh tadsex1h 10.2.65. reg e8h: i nterval update time for fuel gauge percentage setting ?eoasdh tadsex11h bit description r/w default value ap1 battery capacity setting jmhlax1/ mx 1 bit description r/w default value ap g byt jahhefe nytef adaff hbfe7byd6 7ehhmrc7 3 1111p3333 x 4?p1? mx 3131 0p1 byt jahhefe nytef adaff hbfe7byd6 7ehhmrc7 1111p3333 x 4?p34? mx 1111 bit description r/w default value ap 0 reserved and unchangeable mx 111p017 ; ; ;
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 55 10.2.66. reg e9h: fuel gauge calibration interval setting default value 00h 10.2.67. reg ech: coulomb counter percentage of electricity calibration points setting default value 00h bit description r/w default value 7 00-60s 01-120s 10-15s 11-30s rw 0 6 rw 0 5:0 reserved and unchangeable bit description r/w default value 7 :3 reserved and unchangeable 2 when ocv power percentage is less than or equal following settings begin calibration fuel gauge 000-reg_e6_[3:0] +5 001-reg_e6_[3:0] +6 010-reg_e6_[3:0] +7 011-reg_e6_[3:0] +8 100-reg_e6_[3:0] +1 101-reg_e6_[3:0] +2 110-reg_e6_[3:0] +3 111-reg_e6_[3:0] +4 rw 0 1 rw 0 0 rw 0
AXP223 pmic optimized for multi-core high-performance system AXP223 datasheet r evision 1.1 copyright ? 2013 x - p owers limited. all rights r eser v ed. p age 56 package

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